1. Field of the Invention
The invention relates to a memory storage device and a read/write method thereof, and more particularly to a memory storage device and a read/write method for improving efficiency thereof.
2. Description of the Prior Art
Recently with the rapidly development of computer, communication, and consumer electronic, it is almost a prerequisite function of being media of storing data by the build-in flash memory or accessing the external memory card. Hence, the speed of reading and writing the storage media is an important consideration when the users purchase these 3C products because the frequency and quantity of accessing the data are increased day by day.
There are some advantages of the flash memory such as small size, great capacity, low consumption, non-volatile property, enduring vibration, and etc., however, there are two electric limitations of without directly rewriting and limitation of erasing times. Wherein “without directly rewriting” means that the data sector in the original position has to be erased before the new data are stored so that the new data can be rewritten. In addition, the time of erasing operation and resetting all of the memory units is longer than that reading or writing operation. Take TOSHIBA TH58NVG1S3AFT05 2 Gbit for example, its reading time is 50 ns, writing time is 200 us, but erasing time is up to 2 ms.
Reference is shown as in FIG. 1 which is a schematic view of an architecture of a flash memory applied according to the prior art. An external system 10 of the host send a logic block address to a control unit 20 to record the logical block address and the physical block address in the flash memory 30 according to a logical/physical block address map table 2 after the control unit 20 communicates to a flash memory 30. And the prior art can avoid searching all addresses from beginning to end for getting the related logical block address while accessing the data every time.
Reference is shown as in FIG. 2 which is a schematic view of a relation between a physical block address and a logical block address in a flash memory and a logical/physical block address map table built by the relation according to the prior art. The logical/physical block address map table 21 is built after the system is boosted and a SRAM can be designed to store and record the logical/physical block address map table 21 so as to find rapidly the physical block address is corresponded to the logical block address as long as searching the logical/physical block address map table 21 in the SRAM. For the flash memory 30, the writing time is longer than the reading time and it has to consider whether the written address has been filled or not when the data are written in the flash memory 30. If the written address has been filled, the data written from the external system 10 have to be written to a new available free space, and move the data in the original block address to the new block and update the logical/physical block address map table 21 so that the physical block address can be mapped by the logical block address.
In the flash memory specification, however, the relation between the physical block address and the logical block address isn't linear so that it doesn't obtain directly the logical block address according to the physical block address. Hence, it has to collect the data in original written block address before the data in the flash memory 30 are moved, and update the logical/physical block address map table 21 to be designated to the new physical block address after the data are moved. For the above-mentioned reason, if the operations of collecting, moving and address-designating are more frequent, it will increase the times of erasing, moving, and writing so as to influence the whole efficiency.
The inventor of the present invention recognizes the above shortage should be improved and special effort has been made to research this field. The present invention is presented with reasonable design to resolve the above problems.